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4-wire serial interface real-time clock ic s with voltage monitoring function r 5c348a/b electronic devices division no.ea-054-9908 application manual
no tice 1. the products and the product specifications described in this application manual are subject to change or discontinuation of production without notice for reasons such as improvement. therefore, before deciding to use the products, please refer to ricoh sales representatives for the latest information thereon. 2. this application manual may not be copied or otherwise reproduced in whole or in part without prior written consent of ricoh. 3. please be sure to take any necessary formalities under relevant laws or regulations before exporting or otherwise taking out of your country the products or the technical information described herein. 4. the technical information described in this application manual shows typical characteristics of and example application circuits for the products. the release of such information is not to be construed as a warranty of or a grant of license under ricoh's or any third party's intellectual property rights or any other rights. 5. the products listed in this document are intended and designed for use as general electronic components in standard applications (office equipment, computer equipment, measuring instruments, consumer electronic products, amusement equipment etc.). those customers intending to use a product in an application requiring extreme quality and reliability, for example, in a highly specific application where the failure or misoperation of the product could result in human injury or death (aircraft, spacevehicle, nuclear reactor control system, traffic control system, automotive and transportation equipment, combustion equipment, safety devices, life support system etc.) should first contact us. 6. we are making our continuous effort to improve the quality and reliability of our products, but semiconductor products are likely to fail with certain probability. in order prevent any injury to persons or damages to property resulting from such failure, customers should be careful enough to incorporate safety measures in their design, such as redundancy feature, fire-containment feature and fail-safe feature. we do not assume any liability or responsibility for any loss or damage arising from misuse or inappropriate use of the products. 7. anti-radiation design is not implemented in the products described in this application manual. 8. please contact ricoh sales representatives should you have any questions or comments concerning the products or the technical information. june 1995
outline ...................................................................................................... 1 fea tures .................................................................................................. 1 block dia gram ........................................................................................ 2 applica tions ............................................................................................. 2 selection guide ....................................................................................... 2 pin configura tion ................................................................................... 2 pin descriptions ...................................................................................... 3 absolute maximum ra tings ................................................................... 4 recommended opera ting conditions ................................................. 4 dc electrical chara cteristics ........................................................... 5 a c electrical chara cteristics ........................................................... 6 general description .............................................................................. 7 functional descriptions ...................................................................... 9 1. address mapping ......................................................................................... 9 2. register settings ........................................................................................ 10 usa ges ..................................................................................................... 22 1. data t r ansf er f or mats ................................................................................. 22 2. configur ation of oscillation circuit and correction of time count de viations ................. 28 3. oscillation halt sensing and supply v oltage monitor ing .......................................... 33 4. alar m and p er iodic interr upt ........................................................................... 35 5. 32-khz cloc k output ................................................................................... 38 6. t ypical applications .................................................................................... 39 7. t ypical char acter istics ................................................................................. 42 8. t ypical softw are-based oper ations .................................................................. 44 p a cka ge dimensions ............................................................................. 48 t aping specifica tions ........................................................................... 49 r 5c348a/b applica tion manu al contents
1 4-wire serial interf a ce real-time clock ic s with v ol t a ge monit oring function r 5c348a/b outline the r 5c348a/b are cmos real-time clock ics connected to the cpu by four signal lines ce (chip enable), sclk (serial clock), si (serial input), and so (serial output) and configured to perform serial transmission of time and calendar data to the cpu. the periodic interrupt circuit is configured to generate interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1 month. the 2 alarm circuits generate interrupt signals at preset times. the oscillation circuit is driven under constant voltage so that fluctuations in oscillation frequency due to voltage are small and supply current is also small (typ. 0.35 a for the r 5c348a and 0.55 a for the r 5c348b at 3 volts). the oscillation halt sensing circuit can be used to judge the validity of internal data in such events as power-on. the supply voltage monitoring circuit is configured to record a drop in supply voltage below two selectable supply voltage monitoring threshold settings. the 32-khz clock output function (nch. open drain) is intended to output sub-clock pulses for the external microcomputer. the oscillation adjustment circuit is intended to adjust time counts with high precision by correcting deviations in the oscillation frequency of the crystal oscillator. the 32-khz clock circuit can be disabled by certain register settings for the r 5c348a but cannot be disabled by any register settings for the r 5c348b. both these models come in an ultra-compact 10-pin ssop (rs5c348a/b with a height of 1.25mm and a pin pitch of 0.5mm) and 10-pin ssop-g(rv5c348a/b with a height of 1.2mm and a pin pitch of 0.5mm.) fea tures timekeeping supply voltage ranging from 1.45 to 5.5 volts low supply current: typ. 0.35 a (max. 0.8 a) at 3 volts (at 25 ?c ) for the r 5c348a typ. 0.55 a (max. 1.0 a) at 3 volts (at 25 ?c ) for the r 5c348b only four signal lines (ce, sclk, si, and so) required for connection to the cpu. maximum clock frequency of 2mhz (with v dd of 5 volts) time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months, days, and weeks) (in bcd format) 1900/2000 identification bit for year 2000 compliance interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month) to the cpu and provided with an interrupt flag and an interrupt halt circuit 2 alarm circuits (alarm_w for week, hour, and minute alarm settings and alarm_d for hour and minute alarm settings) 32-khz clock circuit (nch. open drain output) the r 5c348a is designed to disable 32-khz clock output in response to a command from the host computer and the r 5c348b is designed to keep 32-khz output enabled. oscillation halt sensing circuit which can be used to judge the validity of internal data supply voltage monitoring circuit with two supply voltage monitoring threshold settings automatic identification of leap years up to the year 2099 selectable 12-hour and 24-hour mode settings built-in oscillation stabilization capacitors (c g and c d ) high precision oscillation adjustment circuit cmos process ultra-compact 10-pin ssop(rs5c348a/b) 10-pin ssop-g(rv5c348a/b)
r 5c348a/b 2 block dia gram c o m p a r a t o r _ w a l a r m _ w r e g i s t e r ( m i n , h o u r , w e e k ) a l a r m _ d r e g i s t e r ( m i n , h o u r ) c o m p a r a t o r _ d t i m e c o u n t e r ( s e c , m i n , h o u r , w e e k , d a y , m o n t h , y e a r ) a d d r e s s r e g i s t e r a d d r e s s d e c o d e r s h i f t r e g i s t e r i n t e r r u p t c o n t r o l 3 2 k h z o u t p u t c o n t r o l d i v i d e r c o r r e c - t i o n d i v o s c o s c i n 3 2 k o u t o s c o u t o s c d e t e c t i / o c o n t r o l v s s s c l k s i s o c e v d d i n t r v o l t a g e d e t e c t pin configura tion 3 2 k o u t 1 s c l k 2 s o 3 v s s s i v d d o s c i n o s c o u t c e i n t r 4 5 8 9 1 0 7 6 ?10-pin ssop-g, 10-pin ssop applica tions ?communication devices (multi function phone, portable phone, phs or pager) ?oa devices (fax, portable fax) ?computer (desk-top and mobile pc, portable word-processor, pda, electric note or video game) ?av components (portable audio unit, video camera,camera, digital camera or remote controller) ?home appliances (rice cooker, electric oven) ?other (car navigation system, multi-function watch) package 32-khz clock output rs5c348a controllable by command rs5c348b keeping output enabled rv5c348a controllable by command rv5c348b keeping output enabled selection guide 10-pin ssop (pitch 0.5mm, height 1.25mm, size 6.4 3.5mm) 10-pin ssop-g (pitch 0.5mm, height 1.20mm, size 4.0 2.9mm) pin configura tion
3 r 5c348a/b pin descriptions pin no. symbol item description 7 ce chip enable input the ce pin is used for interfacing with the cpu. should be held high to allow access to the cpu. incorporates a pull-down resistor. should be held low or open when the cpu is powered off. allows a maximum input voltage of 5.5 volts regardless of supply voltage. 2 sclk serial clock input the sclk pin is used to input clock pulses synchronizing the input and output of data to and from the si and so pins. allows a maximum input voltage of 5.5 volts regardless of supply voltage. 4 si serial input the si pin is used to input data intended for writing in synchronization with the sclk pin. cmos input. allows a maximum input voltage of 5.5 volts regardless of supply voltage. 3 so serial output the so pin is used to output data intended for reading in synchronization with the sclk pin. cmos output. 6 intr interrupt output the intr pin is used to output periodic interrupt signals to the cpu and alarm interrupt signals. disabled at power-on from 0 volts. nch. open drain output. 1 32kout 32-khz clock output the 32kout pin is used to output 32.768-khz clock pulses. enabled at power-on from 0 volts. nch. open drain output. the r 5c348a is designed to be disabled 32-khz clock output in response to a command from the host computer and the r 5c348b is designed to keep 32-khz output enabled. the oscin and oscout pins are used to connect the 32.768-khz crystal oscillator (with all other oscillation circuit components built into the r 5c348a/b). the vdd pin is connected to the power supply. the vss pin is grounded. 9 oscin oscillatory circuit 8 oscout input/output 10 vdd positive power supply input 5 vss negative power supply input
r 5c348a/b 4 absolute maximum ra tings symbol item conditions ratings unit v dd supply voltage ?.3 to +6.5 v v i input voltage 2 si, sclk, ce ?.3 to +6.5 v v o output voltage 1 so ?.3 to v dd +0.3 v output voltage 2 intr, 32kout ?.3 to +6.5 p d power dissipation topt=25?c 300 mw topt operating temperature ?0 to +85 ?c tstg storage temperature ?5 to +125 ?c (vss=0v) absolute maximum ratings absolute maximum ratings are threshold limit values that must not be exceeded even for an instant under any conditions. moreover, such values for any two items must not be reached simultaneously. operation above these absolute maximum ratings may cause degradation or permanent damage to the device. these are stress ratings only and do not necessarily imply functional operation below these limits. recommended opera ting conditions (vss=0v,topt=?0 to +85 ?c) symbol item conditions min. typ. max. unit v dd supply voltage 2.0 5.5 v v clk timekeeping voltage 1.45 5.5 v f xt oscillation frequency 32.768 khz v pup pull-up voltage intr, 32kout 5.5 v
5 r 5c348a/b dc electrical chara cteristics symbol item pin name conditions min. typ. max. unit v ih ??input voltage sclk,ce, si v dd =2.5 to 5.5v 0.8v dd 5.5 v v il ??input voltage ?.3 0.2v dd i oh ??output current so v oh =v dd ?.5v ?.5 i ol1 ??output current intr, 32kout (r 5c348a) v ol =0.4v 2 ma i ol2 so,32kout (r 5c348b) 0.5 i il input leakage current sclk, si v i =5.5v or vss ? 1 a v dd =5.5v r dnce pull-down resistance ce 40 120 400 k i oz1 output off-state so vo=5.5v or vss ? 1 a leakage current v dd =5.5v i oz2 32kout, intr v o =5.5v ? 1 i dd v dd =3v,ce=open ( r 5c348a) v dd output=open 0.35 0.8 standby current 32kout=off mode * 1 a i dd v dd =3v,ce=open ( r 5c348b) v dd output=open 0.55 1.0 32kout=on mode v deth supply voltage monitoring v dd topt=?0 to +70?c 1.90 2.10 2.30 v voltage ( ? ) v detl supply voltage monitoring v dd topt=?0 to +70 ?c 1.45 1.60 1.80 v voltage ( ? ) c g internal oscillation capacitance 1 oscin 12 pf c d internal oscillation capacitance 2 oscout 12 unless otherwise specifie d : vss=0v,v dd =3v,topt=?0 to +85 ?c * 1) for standby current for outputting 32.768-khz clock pulses from the 32kout pin, see ?sages, 7. typical characteristics?
r 5c348a/b 6 symbol item conditions v dd 3 2.0v v dd 3 4.5 unit min. typ. max. min. typ. max. t ces ce set-up time 400 200 ns t ceh ce hold time 400 200 ns t cr ce recovery time 62 62 s f sclk sclk clock frequency 1.0 2.0 mhz t ckh sclk clock ??time 400 200 ns t ckl sclk clock ??time 400 200 ns t cks sclk set-up time 200 100 ns t rd data output delay time 300 150 ns t rz data output floating time 300 150 ns t cez data output floating time 300 150 ns after falling of ce t ds input data set-up time 200 100 ns t dh input data hold time 200 100 ns a c electrical chara cteristics unless otherwise specified : vss=0v,topt=?0 to +85 ?c input/output condition : v ih =0.8 v dd , v il =0.2 v dd , v oh =0.8 v dd , v ol =0.2 v dd , c l =50pf c e s c l k s i s o t c k h t c k l t c k s t c e s t d s t d h t r d t r d t r z t c e z t c e h t c r * ) for read/write timing, see ?sages, 1.5 considerations in reading and writing time data?
7 r 5c348a/b general description 1. inter face with cpu the r 5c348a/b are connected to the cpu by four signal lines ce (chip enable), sclk (serial clock), si (serial input), and so (serial output), through which they read and write data from and to the cpu. the cpu can access when the ce pin is held high. access clock pulses have a maximum frequency of 2mhz (at 5 volts), allowing high- speed data transfer to the cpu. 2. clock and calendar function the r 5c348a/b read and write time data from and to the cpu in units ranging from seconds to the last two digits of the calendar year. the calendar year will automatically be identified as a leap year when its last two digits are a multiple of 4. also available is the 1900/2000 identification bit for year 2000 compliance. consequently, leap years up to the year 2099 can automatically be identified as such. * ) the year 2000 is a leap year while the year 2100 is not a leap year. 3. alar m function the r 5c348a/b incorporate an alarm circuit configured to generate interrupt signals to the cpu for output from the intr pin at preset times. the alarm circuit allows two types of alarm settings specified by the alarm_w registers and the alarm_d registers. the alarm_w registers allow week, hour, and minute alarm settings including combinations of multiple day-of-week settings such as ?onday, wednesday, and friday?and ?aturday and sunday? the alarm_d registers allow hour and minute alarm settings. the current alarm settings specified by these two registers can be checked from the cpu by using a polling function. 4. high-pr ecision oscillation adjustment function the r 5c348a/b have built-in oscillation stabilization capacitors (c g and c d ), which can be connected to an external crystal oscillator to configure an oscillation circuit. to correct deviations in the oscillation frequency of the crystal oscillator, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss (up to 1.5ppm at 25?c) from the cpu within a maximum range of approximately 189ppm in increments of approximately 3ppm. such oscillation frequency adjustment in each system has the following advantages: allows timekeeping with much higher precision than conventional real-time clocks while using a crysta l oscillator with a wide range of precision variations. corrects seasonal frequency deviations through seasonal oscillation adjustment. allows timekeeping with higher precision particularly in systems with a temperature sensing function through oscillation adjustment in tune with temperature fluctuations.
r 5c348a/b 8 5. oscillation halt sensing function and supply v oltage monitoring function the r 5c348a/b incorporate an oscillation halt sensing circuit equipped with internal registers configured to record any past oscillation halt, thereby identifying whether they are powered on from 0 volts or battery backed-up. as such, the oscillation halt sensing circuit is useful for judging the validity of time data. the r 5c348a/b also incorporate a supply voltage monitoring circuit equipped with internal registers configured to record any drop in supply voltage below a certain threshold value. supply voltage monitoring threshold settings can be selected between 2.1 and 1.6 volts through internal register settings. the oscillation halt sensing circuit is configured to confirm the established invalidation of time data in contrast to the supply voltage monitoring circuit intended to confirm the potential invalidation of time data. further, the supply voltage monitoring circuit can be applied to battery supply voltage monitoring. 6. periodic inter r upt function the r 5c348a/b incorporate a periodic interrupt circuit configured to generate periodic interrupt signals aside from interrupt signals generated by the alarm circuit for output from the intr pin. periodic interrupt signals have five selectable frequency settings of 2hz (once per 0.5 seconds), 1hz (once per 1 second), 1/60hz (once per 1 minute), 1/3600hz (once per 1 hour), and monthly (the first day of every month). further, periodic interrupt signals also have two selectable waveforms of a normal pulse form (with a frequency of 2hz or 1hz) and special form adapted to interruption from the cpu in the level mode (with second, minute, hour, and month interrupts). the register records of periodic interrupt signals can be monitored by using a polling function. 7. 32-khz clock output function the r 5c348a/b incorporate a 32-khz clock circuit configured to generate clock pulses with the oscillation frequency of a 32.768-khz crystal oscillator for output from the 32kout pin (nch. open drain output). for the r 5c348a, the 32-khz clock output can be disabled by certain register settings. but it cannot be disabled without manipulation of any two registers with different addresses, to prevent disabling in such events as the runaway of the cpu. for the r 5c348b, however, the 32-khz clock circuit cannot be disabled by any register settings. for both the r 5c348a and the r 5c348b alike, the 32-khz clock circuit is enabled at power-on.
9 r 5c348a/b 0 0 0 0 0 second counter * 2 s 40 s 20 s 10 s 8 s 4 s 2 s 1 1 0 0 0 1 minute counter m 40 m 20 m 10 m 8 m 4 m 2 m 1 2 0 0 1 0 hour counter h 20 h 10 h 8 h 4 h 2 h 1 p/a 3 0 0 1 1 day-of-week counter w 4 w 2 w 1 4 0 1 0 0 day-of-month counter d 20 d 10 d 8 d 4 d 2 d 1 5 0 1 0 1 month counter and century bit 19/20 mo 10 mo 8 mo 4 mo 2 mo 1 6 0 1 1 0 year counter y 80 y 40 y 20 y 10 y 8 y 4 y 2 y 1 7 0 1 1 1 oscillation adjustment register * 3 (0) * 4 f 6 f 5 f 4 f 3 f 2 f 1 f 0 8 1 0 0 0 alarm_w (minute register) wm 40 wm 20 wm 10 wm 8 wm 4 wm 2 wm 1 9 1 0 0 1 alarm_w (hour register) wh 20 wh 10 wh 8 wh 4 wh 2 wh 1 wp/a a 1 0 1 0 alarm_w (day-of-week register ) ww 6 ww 5 ww 4 ww 3 ww 2 ww 1 ww 0 b 1 0 1 1 alarm_d (minute register) dm 40 dm 20 dm 10 dm 8 dm 4 dm 2 dm 1 c 1 1 0 0 alarm_d (hour register) dh 20 dh 10 dh 8 dh 4 dh 2 dh 1 dp/a d 1 1 0 1 e 1 1 1 0 control register 1 * 3 wale dale 12/24 clen2 * 5 test ct 2 ct 1 ct 0 f 1 1 1 1 control register 2 * 3 vdsl vdet scratch1 xstp clen1 * 5 ctfg wafg dafg d3 d2 d1 d0 address a 3 a 2 a 1 a 0 register d4 d5 d6 d7 functional descriptions 1. ad dress mapping * 1) all the data listed above accept both reading and writing. * 2) the data marked with ?is invalid for writing and reset to 0 for reading. * 3) when the xstp bit is set to 1 in control register 2, all the bits are reset to 0 in oscillation adjustment register 1, control register 1 and control register 2 excluding the xstp bit. * 4) writing to the oscillation adjustment register requires zero filling the (0) bit. * 5) these bit names apply to the r 5c348a. for the r 5c348b the bit names are scratch2 and scratch3, respectively. data * 1
r 5c348a/b 10 wale, dale description 0 disabling the alarm interrupt circuit (under the control of the settings of the alarm_w registers and the alarm_d registers). 1 enabling the alarm interrupt circuit (under the control of the settings of the alarm_w registers and the alarm_d registers) d7 d6 d5 d4 d3 d2 d1 d0 wale dale 12/24 clen2 * 2 test ct 2 ct 1 ct 0 wale dale 12/24 clen2 * 2 test ct 2 ct 1 ct 0 0 0 0 0 0 0 0 0 (for writing) (for reading) default settings * 1 (default setting) 2. register settings 2.1 contr ol register 1 (at ad dress eh) * 1) default settings: default value means read/written values when the xstp bit is set to ??due to power-on from 0 volts or supp ly voltage drop. * 2) this bit name applies to the r 5c348a only. for the r 5c348b the bit name is scratch3. 2.1-1 w ale and d ale alarm_w enable bit and alarm_d enable bit 2.1-2 12/24 12-/24-hour mode selection bit 12/24 description 0 selecting the 12-hour mode with a.m. and p.m. indications. 1 selecting the 24-hour mode setting the 12/24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively. t able of t ime digit indications 24-hour mode 12-hour mode 24-hour mode 12-hour mode 00 12 (am12) 12 32 (pm12) 01 01 (am 1) 13 21 (pm 1) 02 02 (am 2) 14 22 (pm 2) 03 03 (am 3) 15 23 (pm 3) 04 04 (am 4) 16 24 (pm 4) 05 05 (am 5) 17 25 (pm 5) 06 06 (am 6) 18 26 (pm 6) 07 07 (am 7) 19 27 (pm 7) 08 08 (am 8) 20 28 (pm 8) 09 09 (am 9) 21 29 (pm 9) 10 10 (am10) 22 30 (pm10) 11 11 (am11) 23 31 (pm11) * ) setting the 12/24 bit should precede writing time data. (default setting)
11 r 5c348a/b test settings 0 normal operation mode 1 test mode 2.1-4 test test bit (default setting) the test bit is used only for testing in the factory and should normally be set to 0. 2.1-3 clen2 ( r 5c348a) 32khz clock output bit 2 clen2 ( r 5c348a) description 0 enabling the 32-khz clock circuit 1 disabling the 32-khz clock circuit (default setting) for the r 5c348a, setting the clen2 bit or the clen1 bit (d3 in the control register 2) to 0 specifies generating clock pulses with the oscillation frequency of the 32.768-khz crystal oscillator for output from the 32kout pin. conversely, setting both the clen1 and the clen2 bit to 1 specifies disabling (?? such output. scra tch3 ( r 5c348b) scratch bit 3 scratch3 ( r 5c348b) description 0 1 (default setting) for the r 5c348b, this bit is intended for scratching and accepts the reading and writing of 0 and 1. the scratch3 bit will be set to 0 when the xstp bit is set to 1 in control register 2.
r 5c348a/b 12 2.1-5 ct 2 , ct 1 , and ct 0 periodic interrupt selection bits ct 2 ct 1 ct 0 description waveform mode interrupt cycle and fall timing 0 0 0 off (?? 0 0 1 fixed at low (?? 0 1 0 pulse mode 2hz (duty cycle of 50%) 0 1 1 pulse mode 1hz (duty cycle of 50%) 1 0 0 level mode once per 1 second (synchronized with second counter increment) 1 0 1 level mode once per minute (at 00 seconds of every minute) 1 1 0 level mode once per hour (at 00 minutes and 00 seconds of every hour) 1 1 1 level mode once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month) (default setting) 1) pulse mode: 2-hz and 1-hz clock pulses are output in synchronization with the increment of the second counter as illustrated in the timing chart on the next page. 2) level mode: periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1 hour, and 1 month. the increment of the second counter is synchronized with the falling edge of periodic interrupt signals. for example, periodic interrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increment of the second counter as illustrated in the timing chart on the next page. 3) when the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20 seconds as follows: pulse mode: the ??period of output pulses will increment or decrement by a maximum of 3.784ms. for example, 1-hz clock pulses will have a duty cycle of 50 0.3784%. level mode: a periodic interrupt cycle of 1 second will increment or decrement by a maximum of 3.784ms.
13 r 5c348a/b relation betw een the mode w a v ef or m and the ctfg bit ?pulse mode a p p r o x . 9 2 s c t f g b i t i n t r p i n ( i n c r e m e n t o f s e c o n d c o u n t e r ) r e w r i t i n g o f t h e s e c o n d c o u n t e r ?level mode s e t t i n g c t f g b i t t o 0 ( i n c r e m e n t o f s e c o n d c o u n t e r ) ( i n c r e m e n t o f s e c o n d c o u n t e r ) ( i n c r e m e n t o f s e c o n d c o u n t e r ) c t f g b i t i n t r p i n s e t t i n g c t f g b i t t o 0 * ) in the pulse mode, the increment of the second counter is delayed by approximately 92 s from the falling edge of clock pulses. consequently, time readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second. rewriting the second counter will reset the other time counters of less than 1 second, driving the intr pin low.
r 5c348a/b 14 vdsl description 0 selecting the supply voltage monitoring threshold setting of 2.1 volts. 1 selecting the supply voltage monitoring threshold setting of 1.6 volts. 2.2-1 vdsl supply voltage monitoring threshold selection bit the vdsl bit is intended to select the supply voltage monitoring threshold settings. vdet description 0 indicating supply voltage above the supply voltage monitoring threshold settings. 1 indicating supply voltage below the supply voltage monitoring threshold settings. 2.2-2 vdet supply voltage monitoring result indication bit (default setting) once the vdet bit is set to 1, the supply voltage monitoring circuit will be disabled while the vdet bit will hold the setting of 1. the vdet bit accepts only the writing of 0, which restarts the supply voltage monitoring circuit. conversely, setting the vdet bit to 1 causes no event. d7 d6 d5 d4 d3 d2 d1 d0 vdsl vdet scratch1 xstp clen1 * 2 ctfg wafg dafg vdsl vdet scratch1 xstp clen1 * 2 ctfg wafg dafg 0 0 0 1 0 0 0 0 2.2 contr ol register 2 (at ad dress fh) (for write operation) (for read operation) default setting* 1 scratch1 description 0 1 2.2-3 scra tch1 scratch bit 1 (default settings) the scratch1 bit is intended for scratching and accepts the reading and writing of 0 and 1. the scratch1 bit will be set to 0 when the xstp bit is set to 1 in the control register 2. (default setting) * 1) default settings: default value means read/written values when the xstp bit is set to ??due to power-on from 0 volts or suppl y voltage drop. * 2) this bit name applies to the r 5c348a only. for the r 5c348b the bit name is scratch2.
15 r 5c348a/b 2.2-4 xstp oscillation halt sensing bit clen1 description 0 enabling the 32-khz clock output 1 disabling the 32-khz clock output 2.2-5 clen1 ( r 5c348a) 32-khz clock output bit 1 (default setting) for the r 5c348a, setting the clen1 bit or the clen2 bit (d4 in control register 1) to 0 specifies generating clock pulses with the oscillation frequency of the 32.768-khz crystal oscillator for output from the 32kout pin. conversely, setting both the clen1 bit and the clen2 bit to 1 specifies disabling (?? such output. the xstp bit is for sensing a halt in the oscillation of the crystal oscillator. the oscillation halt sensing circuit operates only when the ce pin is ?? the xstp bit will be set to 1 once a halt in the oscillation of the crystal oscillator is caused by such events as power-on from 0 volts and a drop in supply voltage. the xstp bit will hold the setting of 1 even after the restart of oscillation. as such, the xstp bit can be applied to judge the validity of clock and calendar data after power-on or a drop in supply voltage. when the xstp bit is set to 1, all bits will be reset to 0 in the oscillation adjustment register, control register 1, and control register 2, stopping the output from the intr pin and starting the output of 32.768-khz clock pulses from the 32kout pin. the xstp bit accepts only the writing of 0, which restarts the oscillation halt sensing circuit. conversely, setting the xstp bit to 1 causes no event. it is recommendable to frequently check the xstp bit for setting errors or data garbles, which may seriously affect the operation of the r 5c348a/b. xstp description 0 sensing a normal condition of oscillation 1 sensing a halt of oscillation (default setting) scratch2( r 5c348b) description 0 1 scra tch2 ( r 5c348b) scratch bit 2 (default setting) for the r 5c348b, this bit is a scratch bit. the scratch2 bit will accept the reading and writing of 0 and 1. the scratch2 bit will set to 0 when the xstp bit is set to 1.
r 5c348a/b 16 wafg, dafg description 0 indicating a mismatch between current time and preset alarm time 1 indicating a match between current time and preset alarm time 2.2-7 w afg and d afg alarm_w flag bit and alarm_d flag bit (default setting) the wafg and dafg bits are valid only when the wale and dale bits have the setting of 1, which is caused approximately 61 s after any match between current time and preset alarm time specified by the alarm_w registers and the alarm_d registers. the wafg and dafg bits accept only the writing of 0, which disables (?? the intr pin until it is enabled (?? again at the next preset alarm time. conversely, setting the wafg and dafg bits to 1 causes no event. the wafg and dafg bits will have the reading of 0 when the alarm interrupt circuit is disabled with the wale and dale bits set to 0. the settings of the wafg and dafg bits are synchronized with the output of the intr pin as shown in the timing chart below. output relationships betw een the w afg or d afg bit and intr w r i t i n g o f 0 t o w a f g ( d a f g ) b i t w r i t i n g o f 0 t o w a f g ( d a f g ) b i t ( m a t c h b e t w e e n c u r r e n t t i m e a n d p r e s e t a l a r m t i m e ) ( m a t c h b e t w e e n c u r r e n t t i m e a n d p r e s e t a l a r m t i m e ) ( m a t c h b e t w e e n c u r r e n t t i m e a n d p r e s e t a l a r m t i m e ) s e t t i n g s o f w a f g ( d a f g ) b i t o u t p u t o f i n t r p i n a p p r o x . 6 1 s a p p r o x . 6 1 s ctfg description 0 periodic interrupt output ??(off) 1 periodic interrupt output ??(on) 2.2-6 ctfg periodic interrupt flag bit (default setting) the ctfg bit is set to 1 when the periodic interrupt signals are output from the intr pin (??. the ctfg bit accepts only the writing of 0 in the level mode, which disables (?? the intr pin until it is enabled (?? again in the next interrupt cycle. conversely, setting the ctfg bit to 1 causes no event.
17 r 5c348a/b 2.3 time counter s (at ad dresses 0h to 2h) time digit display (bcd format) as follows: the second digits range from 00 to 59 and are carried to the minute digit in transition from 59 to 00. the minute digits range from 00 to 59 and are carried to the hour digits in transition from 59 to 00. the hour digits range as shown in ?.1-2 12/24: 12-/ 24-hour mode selection bit?and are carried to the day-of-month and day-of-week digits in transition from pm11 to am12 or from 23 to 00. any writing to the second counter resets divider units of less than 1 second. any carry from lower digits with the writing of non-existent time may cause the time counters to malfunction. therefore, such incorrect writing should be replaced with the writing of existent time data. 2.3-1 second counter (at address 0h) d7 d6 d5 d4 d3 d2 d1 d0 s 40 s 20 s 10 s 8 s 4 s 2 s 1 0 s 40 s 20 s 10 s 8 s 4 s 2 s 1 0 indefinite indefinite indefinite indefinite indefinite indefinite indefinite (for writing) (for reading) default settings* 2.3-2 min ute counter (at address 1h) d7 d6 d5 d4 d3 d2 d1 d0 m 40 m 20 m 10 m 8 m 4 m 2 m 1 0 m 40 m 20 m 10 m 8 m 4 m 2 m 1 0 indefinite indefinite indefinite indefinite indefinite indefinite indefinite (for writing) (for reading) default settings* 2.3-3 hour counter (at address 2h) d7 d6 d5 d4 d3 d2 d1 d0 p/a or h 20 h 10 h 8 h 4 h 2 h 1 0 0 p/a or h 20 h 10 h 8 h 4 h 2 h 1 0 0 indefinite indefinite indefinite indefinite indefinite indefinite (for writing) (for reading) default settings* * ) default settings: default value means read/written values when the xstp bit is set to ??due to power-on from 0 volts or suppl y voltage drop.
18 2.4 da y-of-week counter (at ad dress 3h) d7 d6 d5 d4 d3 d2 d1 d0 w 4 w 2 w 1 0 0 0 0 0 w 4 w 2 w 1 0 0 0 0 0 indefinite indefinite indefinite (for writing) (for reading) default settings* * ) default settings: default value means read/written values when the xstp bit is set to ??due to power-on from 0 volts or suppl y voltage drop. the day-of-week counter is incremented by 1 when the day-of-week digits are carried to the day-of-month digits. day-of-week display (incremented in septimal notation): (w 4 , w 2 , w 1 ) = (0, 0, 0) ? (0, 0, 1) ? ... ? (1, 1, 0) ? (0, 0, 0) correspondences between days of the week and the day-of-week digits are user-definable (e.g. sunday = 0, 0, 0) the writing of (1, 1, 1) to (w 4 , w 2 , w 1 ) is prohibited except when days of the week are unused. 2.5 calendar counter s (at ad dresses 4h to 6h) the calendar counters are configured to display the calendar digits in bcd format by using the automatic calendar function as follows: the day-of-month digits (d 20 to d 1 ) range from 1 to 31 for january, march, may, july, august, october, and december; from 1 to 30 for april, june, september, and november; from 1 to 29 for february in leap years; from 1 to 28 for february in ordinary years. the day-of-month digits are carried to the month digits in reversion from the last day of the month to 1. the month digits (mo 10 to mo 1 ) range from 1 to 12 and are carried to the year digits in reversion from 12 to 1. the year digits (y 80 to y 1 ) range from 00 to 99 (00, 04, 08, ... , 92, and 96 in leap years) and are carried to the 19/20 digits in reversion from 99 to 00. the 19/20 digits cycle between 0 and 1 in reversion from 99 to 00 in the year digits. any carry from lower digits with the writing of non-existent calendar data may cause the calendar counters to malfunction. therefore, such incorrect writing should be replaced with the writing of existent calendar data. 2.5-1 da y-of-month counter (at address 4h) d7 d6 d5 d4 d3 d2 d1 d0 d 20 d 10 d 8 d 4 d 2 d 1 0 0 d 20 d 10 d 8 d 4 d 2 d 1 0 0 indefinite indefinite indefinite indefinite indefinite indefinite (for writing) (for reading) default settings* 2.5-2 month counter + centur y bit (at address 5h) d7 d6 d5 d4 d3 d2 d1 d0 19/20 mo 10 mo 8 mo 4 mo 2 mo 1 19/20 0 0 mo 10 mo 8 mo 4 mo 2 mo 1 indefinite 0 0 indefinite indefinite indefinite indefinite indefinite (for writing) (for reading) default settings* rs5c348a/b
19 r 5c348a/b 2.5-3 y ear counter (at address 6h) d7 d6 d5 d4 d3 d2 d1 d0 y 80 y 40 y 20 y 10 y 8 y 4 y 2 y 1 y 80 y 40 y 20 y 10 y 8 y 4 y 2 y 1 indefinite indefinite indefinite indefinite indefinite indefinite indefinite indefinite (for writing) (for reading) default settings* 2.6 oscillation adjustment register (at ad dress 7h) d7 d6 d5 d4 d3 d2 d1 d0 (0) f 6 f 5 f 4 f 3 f 2 f 1 f 0 (0) f 6 f 5 f 4 f 3 f 2 f 1 f 0 0 0 0 0 0 0 0 0 (for writing) (for reading) default settings* * ) default settings: default value means read/written values when the xstp bit is set to ??due to power-on from 0 volts or suppl y voltage drop. 2.6-1 (0) bit the (0) bit should be set to 0 to allow writing to the oscillation adjustment register. the (0) bit will be set to 0 when the xstp bit is set to 1 in the control register 2. 2.6-2 f 6 to f 0 bits the oscillation adjustment circuit is configured to change time counts of 1 second on the basis of the settings of the oscillation adjustment register when the second digits read 00, 20, or 40 seconds. normally, the second counter is incremented once per 32768 32.768-khz clock pulses generated by the crystal oscillator. writing to the f 6 to f 0 bits activates the oscillation adjustment circuit. the oscillation adjustment circuit will not operate with the same timing (00, 20, or 40 seconds) as the timing of writing to the oscillation adjustment register. the f6 bit setting of 0 causes an increment of time counts by ((f 5 , f 4 , f 3 , f 2 , f 1 , f 0 ) ?1) 2. the f6 bit setting of 1 causes a decrement of time counts by ((f 5 , f 4 , f 3 , f 2 , f 1 , f 0 ) + 1) 2. the settings of * , 0, 0, 0, 0, 0, * ?( * ?representing either ??or ?? in the f 6 , f 5 , f 4 , f 3 , f 2 , f 1 , and f 0 bits cause neither an increment nor decrement of time counts. example: when the second digits read 00, 20, or 40, the settings of ?, 0, 0, 0, 1, 1, 1?in the f 6 , f 5 , f 4 , f 3 , f 2 , f 1 , and f 0 bits cause an increment of the current time counts of 32768 by (7?) 2 to 32780 (a current time count loss). when the second digits read 00, 20, or 40, the settings of ?, 0, 0, 0, 0, 0, 1?in the f 6 , f 5 , f 4 , f 3 , f 2 , f 1 , and f 0 bits cause neither an increment nor a decrement of the current time counts of 32768. when the second digits read 00, 20, or 40, the settings of ?, 1, 1, 1, 1, 1, 0?in the f 6 , f 5 , f 4 , f 3 , f 2 , f 1 , and f 0 bits cause a decrement of the current time counts of 32768 by (?) 2 to 32764 (a current time count gain). * ) default settings: default value means read/written values when the xstp bit is set to ??due to power-on from 0 volts or suppl y voltage drop.
r 5c348a/b 20 2.7 alarm_w register s (at ad dresses 8h to ah) d7 d6 d5 d4 d3 d2 d1 d0 wm 40 wm 20 wm 10 wm 8 wm 4 wm 2 wm 1 0 wm 40 wm 20 wm 10 wm 8 wm 4 wm 2 wm 1 0 indefinite indefinite indefinite indefinite indefinite indefinite indefinite (for writing) (for reading) default settings* 2.7-1 alar m_w min ute register (at address 8h) d7 d6 d5 d4 d3 d2 d1 d0 wh 20 ,wp/a wh 10 wh 8 wh 4 wh 2 wh 1 0 0 wh 20 ,wp/a wh 10 wh 8 wh 4 wh 2 wh 1 0 0 indefinite indefinite indefinite indefinite indefinite indefinite (for writing) (for reading) default settings* 2.7-2 alar m_w hour register (at address 9h) d7 d6 d5 d4 d3 d2 d1 d0 ww 6 ww 5 ww 4 ww 3 ww 2 ww 1 ww 0 0 ww 6 ww 5 ww 4 ww 3 ww 2 ww 1 ww 0 0 indefinite indefinite indefinite indefinite indefinite indefinite indefinite (for writing) (for reading) default settings* 2.7-3 alar m_w da y-of-w eek register (at address ah) the d5 bit of the alarm_w hour register represents wp/a when the 12-hour mode is selected (0 for a.m. and 1 for p.m.). and wh 20 when the 24-hour mode is selected (tens in the hour digits). the alarm_w registers should not have any non-existent alarm time settings. (note that any mismatch between current time and preset alarm time specified by the alarm_w registers may disable the alarm circuit.) when the 12-hour mode is selected, the hour digits read 12 and 32 for 0 a.m. and 0 p.m., respectively (see ?.1-2 12/24: 12-/24-hour mode selection bit?. ww 0 to ww 6 correspond to w 4 , w 2 , and w 1 of the day-of-week counter with settings ranging from (0, 0, 0) to (1, 1, 0). ww 0 to ww 6 with respective settings of 0 disable the outputs of the alarm_w registers. * ) default settings: default value means read/written values when the xstp bit is set to ??due to power-on from 0 volts or suppl y voltage drop. an increase of two clock pulses once per 20 seconds causes a time count loss of approximately 3ppm (2 / (32768 20 = 3.051ppm). conversely, a decrease of two clock pulses once per 20 seconds causes a time count gain of 3ppm. consequently, deviations in time counts can be corrected with a precision of 1.5ppm. note that the oscillation adjustment circuit is configured to correct deviations in time counts and not the oscillation frequency of the 32.768- khz clock pulses. for further details, see ?sages, 2.4 oscillation adjustment circuit?
21 r 5c348a/b day-of-week 12-hour mode 24-hour mode preset alarm time sun. mon. tue. wed. thu. fri. sat. 10-hour 1-hour 10-min 1-min 10-hour 1-hour 10-min 1-min ww 0 ww 1 ww 2 ww 3 ww 4 ww 5 ww 6 00:00 a.m. on all days 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 01:30 a.m. on all days 1 1 1 1 1 1 1 0 1 3 0 0 1 3 0 11:59 a.m. on all days 1 1 1 1 1 1 1 1 1 5 9 1 1 5 9 00:00 p.m. on 0 1 1 1 1 1 0 3 2 0 0 1 2 0 0 mondays to fridays 01:30 p.m. on sundays 1 0 0 0 0 0 0 2 1 3 0 1 3 3 0 11:59 p.m. on mondays, 0 1 0 1 0 1 0 3 1 5 9 2 3 5 9 wednesdays, and fridays note that the correspondence between ww 0 to ww 6 and the days of the week shown in the above table is only an example and not mandatory. d7 d6 d5 d4 d3 d2 d1 d0 dm 40 dm 20 dm 10 dm 8 dm 4 dm 2 dm 1 0 dm 40 dm 20 dm 10 dm 8 dm 4 dm 2 dm 1 0 indefinite indefinite indefinite indefinite indefinite indefinite indefinite (for writing) (for reading) default settings* 2.8-1 alar m_d min ute register (at address bh) d7 d6 d5 d4 d3 d2 d1 d0 dh 20 ,dp/a dh 10 dh 8 dh 4 dh 2 dh 1 0 0 dh 20 ,dp/a dh 10 dh 8 dh 4 dh 2 dh 1 0 0 indefinite indefinite indefinite indefinite indefinite indefinite (for writing) (for reading) default settings* 2.8-2 alar m_d hour register (at address ch) 2.8 alarm_d register s (at ad dresses bh to ch) * ) default settings: default value means read/written values when the xstp bit is set to ??due to power-on from 0 volts or suppl y voltage drop. the d5 bit represents dp/a when the 12-hour mode is selected (0 for a.m. and 1 for p.m.). and dh 20 when the 24- hour mode is selected (tens in the hour digits). the alarm_d registers should not have any non-existent alarm time settings. (note that any mismatch between current time and preset alarm time specified by the alarm_d registers may disable the alarm circuit.) when the 12-hour mode is selected, the hour digits read 12 and 32 for 0 a.m. and 0 p.m., respectively (see ?.1-2 12/24: 12-/24-hour mode selection bit?. example of alar m t ime setting
r 5c348a/b 22 usa ges 1. data t ransf er formats 1.1 timing between ce pin t ransition and data input/output the r 5c348a/b adopt a 4-wire serial interface by which they use the ce (chip enable), sclk (serial clock), si (serial input), and so (serial output) pins to receive and send data to and from the cpu. the 4-wire serial interface provides two types of input/output timings with which the so pin output and the si pin input are synchronized with the rising and falling edges of the sclk pin input, respectively, and vice versa. the r 5c348a/b are configured to select either one of two different input/output timings depending on the level of the sclk pin in the low to high transition of the ce pin. namely, when the sclk pin is held low in the low to high transition of the ce pin, the models will select the timing with which the so pin output and the si pin input are synchronized with the rising and falling edges of the sclk pin input, respectively, as illustrated in the timing chart below. t c e s t d s t d h t r d c e s c l k s i s o conversely, when the sclk pin is held high in the low to high transition of the ce pin, the models will select the timing with which the so pin output and the si pin input are synchronized with the falling and rising edges of the sclk pin input, respectively as illustrated in the timing chart below. t c e s t d s t d h t r d c e s c l k s i s o
23 r 5c348a/b 1 2 3 4 5 6 7 8 1 2 3 a 3 a 2 a 1 a 0 c 3 c 2 c 1 c 0 d 7 d 6 d 7 d 6 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 c e s c l k s i s o s e t t i n g t h e a d d r e s s p o i n t e r s e t t i n g t h e t r a n s f e r f o r m a t r e g i s t e r w r i t i n g d a t a t r a n s f e r r e a d i n g d a t a t r a n s f e r 1.2 data t ransf er formats data transfer is commenced in the low to high transition of the ce pin input and completed in its high to low transition. data transfer is conducted serially in multiple units of 1 byte (8 bits). the former 4 bits are used to specify in the address pointer a head address with which data transfer is to be commenced from the host. the latter 4 bits are used to select either reading data transfer or writing data transfer and set the transfer format register to specify an appropriate data transfer format. all data transfer formats are designed to transfer the most significant bit (msb) first. two types of data transfer formats are available for reading data transfer and writing data transfer each. 1.3 data t ransf er write formats of the r 5c348a/b 1.3-1 1-b yte wr iting data t r ansf er f or mat the first type of writing data transfer format is designed to transfer 1-byte data at a time and can be selected by specifying in the address pointer a head address with which writing data transfer is to be commenced and then writing the setting of 8h to the transfer format register. this 1-byte writing data transfer can be completed by driving the ce pin low or continued by specifying a new head address in the address pointer and setting the transfer format. example of 1-byte writing data transfer (for writing data to addresses fh and 7h) 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 s p e c i f y i n g f h i n t h e a d d r e s s p o i n t e r s p e c i f y i n g 7 h i n t h e a d d r e s s p o i n t e r w r i t i n g d a t a t o a d d r e s s f h w r i t i n g d a t a t o a d d r e s s 7 h d a t a d a t a d a t a t r a n s f e r f r o m t h e h o s t d a t a t r a n s f e r f r o m t h e r e a l - t i m e c l o c k s c e s i s o s e t t i n g 8 h i n t h e t r a n s f e r f o r m a t r e g i s t e r s e t t i n g 8 h i n t h e t r a n s f e r f o r m a t r e g i s t e r
r 5c348a/b 24 1.3-2 burst wr iting data t r ansf er f or mat the second type of writing data transfer format is designed to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with which writing data transfer is to be commenced and then writing the setting of 0h to the transfer format register. the address pointer is incremented for each transfer of 1-byte data and cycled from fh to 0h. this burst writing data transfer can be completed by driving the ce pin low. example of burst writing data transfer (for writing data to addresses eh, fh, and 0h) 1 1 1 0 0 0 0 0 d a t a d a t a d a t a c e s i s o s p e c i f y i n g e h i n t h e a d d r e s s p o i n t e r w r i t i n g d a t a t o a d d r e s s e h w r i t i n g d a t a t o a d d r e s s f h w r i t i n g d a t a t o a d d r e s s 0 h d a t a t r a n s f e r f r o m t h e h o s t d a t a t r a n s f e r f r o m t h e r e a l - t i m e c l o c k s s e t t i n g 0 h i n t h e t r a n s f e r f o r m a t r e g i s t e r 1 1 1 0 1 0 0 1 c e s i s o d a t a d a t a 0 0 1 0 1 0 0 1 s p e c i f y i n g e h i n t h e a d d r e s s p o i n t e r r e a d i n g d a t a f r o m a d d r e s s e h r e a d i n g d a t a f r o m a d d r e s s 2 h d a t a t r a n s f e r f r o m t h e h o s t d a t a t r a n s f e r f r o m t h e r e a l - t i m e c l o c k s s e t t i n g c h i n t h e t r a n s f e r f o r m a t r e g i s t e r s p e c i f y i n g 2 h i n t h e a d d r e s s p o i n t e r s e t t i n g c h i n t h e t r a n s f e r f o r m a t r e g i s t e r 1. 4 reading data t ransf er formats 1.4-1 1-b yte reading data t r ansf er f or mat the first type of reading data transfer format is designed to transfer 1-byte data at a time and can be selected by specifying in the address pointer a head address with which reading data transfer is to be commenced and then the setting of writing ch to the transfer format register. this 1-byte reading data transfer can be completed by driving the ce pin low or continued by specifying a new head address in the address pointer and setting the transfer format. example of 1-byte reading data transfer (for reading data from addresses eh and 2h)
25 r 5c348a/b 1.4-2 burst reading data t r ansf er f or mat the second type of reading data transfer format is designed to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with which reading data transfer is to be commenced and then writing the setting of 4h to the transfer format register. the address pointer is incremented for each transfer of 1-byte data and cycled from fh to oh. this burst reading data transfer can be completed by driving the ce pin low. example of burst reading data transfer (for reading data from addresses fh, 0h, and 1h) 1 1 1 1 0 0 0 1 d a t a d a t a d a t a c e s i s o s p e c i f y i n g f h i n t h e a d d r e s s p o i n t e r r e a d i n g d a t a f r o m a d d r e s s f h r e a d i n g d a t a f r o m a d d r e s s 0 h r e a d i n g d a t a f r o m a d d r e s s 1 h d a t a t r a n s f e r f r o m t h e h o s t d a t a t r a n s f e r f r o m t h e r e a l - t i m e c l o c k s s e t t i n g 4 h i n t h e t r a n s f e r f o r m a t r e g i s t e r 1 1 1 1 1 0 0 1 c e s i s o d a t a d a t a 1 1 1 1 1 0 0 0 s p e c i f y i n g f h i n t h e a d d r e s s p o i n t e r r e a d i n g d a t a f r o m a d d r e s s f h w r i t i n g d a t a t o a d d r e s s f h d a t a t r a n s f e r f r o m t h e h o s t d a t a t r a n s f e r f r o m t h e r e a l - t i m e c l o c k s s e t t i n g c h i n t h e t r a n s f e r f o r m a t r e g i s t e r s p e c i f y i n g f h i n t h e a d d r e s s p o i n t e r s e t t i n g 8 h i n t h e t r a n s f e r f o r m a t r e g i s t e r 1.4-3 combination of 1-b yte reading and wr iting data t r ansf er f or mats the 1-byte reading and writing data transfer formats can be combined together and further followed by any other data transfer format. example of combination of 1-byte reading and writing data transfer (for reading and writing data from and to address fh) the reading and writing data transfer formats correspond to the settings in the transfer format register as shown in the table below. 1-byte transfer burst (successive) transfer writing data transfer 8h 0h (for writing to real-time clock) (1,0,0,0) (0,0,0,0) reading data transfer ch 4h (for reading from real-time clock) (1,1,0,0) (0,1,0,0)
r 5c348a/b 26 a c t u a l t i m e c e t i m e c o u n t s w i t h i n r e a l - t i m e c l o c k s 1 3 : 5 9 : 5 9 1 4 : 0 0 : 0 0 1 4 : 0 0 : 0 1 1 3 : 5 9 : 5 9 1 4 : 0 0 : 0 0 1 4 : 0 0 : 0 1 m a x . 9 1 s 1.5 considerations in reading and writing time data any carry to the second digits in the process of reading or writing time data may cause reading or writing erroneous time data. for example, suppose a carry out of 13:59:59 into 14:00:00 occurs in the process of reading time data in the middle of shifting from the minute digits to the hour digits. at this moment, the second digits, the minute digits, and the hour digits read 59 seconds, 59 minutes, and 14 hours, respectively (indicating 14:59:59) to cause the reading of time data deviating from actual time virtually 1 hour. a similar error also occurs in writing time data. to prevent such errors in reading and writing time data, the r 5c348a/b have the function of temporarily locking any carry of the time digits during the high interval of the ce pin and unlocking such a carry in its high to low transition. note that a carry of the second digits can be locked for only 1 second, during which time the ce pin should be driven low. the effective use of this function requires the following considerations in reading and writing time data: (1) hold the ce pin high in each session of reading or writing time data. (2) ensure that the high interval of the ce pin lasts within 1 second. should there be any possibility of the host going down in the process of reading or writing time data, make arrangements in the peripheral circuitry as to drive the ce pin low or open at the moment that the host actually goes down. (3) leave a time span of 31 s or more from the low to high transition of the ce pin to the start of access to addresses 0h to 6h in order that any ongoing carry of the time digits may be completed within this time span. (4) leave a time span of 61 s or more from the high to low transition of the ce pin to its low to high transition in order that any ongoing carry of the time digits during the high interval of the ce pin may be adjusted within this time span. (5) the considerations listed in (1), (3), and (4) above are not required when the process of reading or writing time data is obviously free from any carry of the time digits (e.g. reading or writing time data in synchronization with the periodic interrupt function in the level mode or the alarm interrupt function). good and bad examples of reading and writing time data are illustrated on the next page.
27 r 5c348a/b c e s i s o t i m e s p a n o f l e s s t h a n 3 1 s f 0 h d a t a d a t a d a t a d a t a c e s i s o t i m e s p a n o f 3 1 s o r m o r e s p e c i f y i n g f h i n t h e a d d r e s s p o i n t e r w r i t i n g 4 h t o t h e t r a n s f e r f o r m a t r e g i s t e r r e a d i n g f r o m t h e m i n u t e c o u n t e r a t a d d r e s s 1 h r e a d i n g f r o m t h e s e c o n d c o u n t e r a t a d d r e s s 0 h r e a d i n g f r o m t h e c o n t r o l r e g i s t e r 2 a t a d d r e s s f h r e a d i n g f r o m t h e h o u r c o u n t e r a t a d d r e s s 2 h s p e c i f y i n g f h i n t h e a d d r e s s p o i n t e r w r i t i n g 0 h t o t h e t r a n s f e r f o r m a t r e g i s t e r w r i t i n g t o t h e c o n t r o l r e g i s t e r 2 a t a d d r e s s f h w r i t i n g t o t h e m i n u t e c o u n t e r a t a d d r e s s 1 h w r i t i n g t o t h e s e c o n d c o u n t e r a t a d d r e s s 0 h w r i t i n g t o t h e h o u r c o u n t e r a t a d d r e s s 2 h s p e c i f y i n g 0 h i n t h e a d d r e s s p o i n t e r w r i t i n g c h i n t h e t r a n s f e r f o r m a t r e g i s t e r s p e c i f y i n g 1 h i n t h e a d d r e s s p o i n t e r w r i t i n g 4 h i n t h e t r a n s f e r f o r m a t r e g i s t e r r e a d i n g f r o m t h e m i n u t e c o u n t e r a t a d d r e s s 1 h r e a d i n g f r o m t h e s e c o n d c o u n t e r a t a d d r e s s 0 h r e a d i n g f r o m t h e h o u r c o u n t e r a t a d d r e s s 2 h s p e c i f y i n g 0 h i n t h e a d d r e s s p o i n t e r w r i t i n g c h t o t h e t r a n s f e r f o r m a t r e g i s t e r s p e c i f y i n g 0 h i n t h e a d d r e s s p o i n t e r w r i t i n g c h t o t h e t r a n s f e r f o r m a t r e g i s t e r r e a d i n g f r o m t h e s e c o n d c o u n t e r a t a d d r e s s 0 h r e a d i n g f r o m t h e s e c o n d c o u n t e r a t a d d r e s s 0 h f 4 h d a t a d a t a d a t a d a t a c e s i s o t i m e s p a n o f 3 1 s o r m o r e t i m e s p a n o f 3 1 s o r m o r e 0 c h d a t a d a t a d a t a 1 4 h c e s i s o t i m e s p a n o f l e s s t h a n 6 1 s 0 c h d a t a d a t a 0 c h 0 c h d a t a g o o d e x a m p l e a n y a d d r e s s o t h e r t h a n a d d r e s s e s 0 h t o 6 h p e r m i t s o f i m m e d i a t e r e a d i n g o r w r i t i n g w i t h o u t r e q u i r i n g a t i m e s p a n o f 3 1 s . b a d e x a m p l e ( 1 ) : w h e r e t h e c e p i n i s o n c e d r i v e n l o w i n t h e p r o c e s s o f r e a d i n g t i m e d a t a . b a d e x a m p l e ( 2 ) : w h e r e a t i m e s p a n o f l e s s t h a n 3 1 s i s l e f t u n t i l t h e s t a r t o f t h e p r o c e s s o f w r i t i n g t i m e d a t a . b a d e x a m p l e ( 3 ) : w h e r e a t i m e s p a n o f l e s s t h a n 6 1 s i s l e f t b e t w e e n t h e a d j a c e n t p r o c e s s e s o f r e a d i n g t i m e d a t a . d a t a t r a n s f e r f r o m t h e h o s t d a t a t r a n s f e r f r o m t h e r e a l - t i m e c l o c k s
r 5c348a/b 28 2. configuration of oscillation cir cuit and correction of time count de viations 2.1 configuration of oscillating cir cuit typical externally-equipped element x'tal: 32.768khz (r 1 =30k typ.) (c l =6pf to 8pf) standard values of internal elements r f =15m typ. r d =120k typ. c g , c d =12pf typ. the oscillation circuit is driven at a constant voltage of approximately 1.2 volts relative to the level of the v ss pin input. as such, it is configured to generate an oscillating waveform with a peak-to-peak voltage on the order of 1.2 volts on the positive side of the v ss pin input. considerations in handling crystal oscillators generally, crystal oscillators have basic characteristics including an equivalent series resistance (r 1 ) indicating the ease of their oscillation and a load capacitance (c l ) indicating the degree of their center frequency. particularly, crystal oscillators intended for use with the r 5c348a/b are recommended to have a typical r 1 value of 30k and a typical c l value of 6 to 8pf. to confirm these recommended values, contact the manufacturers of crystal oscillators intended for use with these particular models. considerations in installing components around the oscillation circuit 1) install the crystal oscillator in the closest possible vicinity to the real-time clock ics. 2) avoid laying any signal lines or power lines in the vicinity of the oscillation circuit (particularly in the area marked ? a ? ?in the above figure). 3) apply the highest possible insulation resistance between the oscin and oscout pins and the printed circuit board. 4) avoid using any long parallel lines to wire the oscin and oscout pins. 5) take extreme care not to cause condensation, which leads to various problems such as oscillation halt. other relevant considerations 1) for external input of 32.768-khz clock pulses to the oscin pin: dc coupling: prohibited due to an input level mismatch. ac coupling: permissible except that the oscillation halt sensing circuit does not guarantee perfect operation because it may cause sensing errors due to such factors as noise. 2) to maintain stable characteristics of the crystal oscillator, avoid driving any other ic through 32.768-khz clock pulses output from the oscout pin. r 5 c 3 4 8 a / b r f r d c d c g o s c i n o s c o u t 3 2 k h z v d d 1 0 9 8 v d d a
29 r 5c348a/b 2.2 measurement of oscillation frequenc y f r e q u e n c y c o u n t e r r 5 c 3 4 8 a / b 3 2 . 7 6 8 k h z o s c i n o s c o u t v d d v s s 3 2 k o u t * 1) the r 5c348a is configured to generate 32.768-khz clock pulses for output from the 32kout pin at power-on conditionally on setting th e xstp bit to 1 in the control register 2. conversely, the r 5c348b is configured to generate 32-khz clock pulses for output from the 32kout pin regardless of any internal register settings including the xstp bit setting in the control register 2. * 2) a frequency counter with 6 (more preferably 7) or more digits on the order of 1ppm is recommended for use in the measurement of the oscillation frequency of the oscillation circuit. * 3) the 32kout pin should be connected to the v dd pin with a pull-up resistor. 2.3 adjustment of oscillation frequenc y the oscillation frequency of the oscillation circuit can be adjusted by varying procedures depending on the usage of the r 5c348a/b in the system into which they are to be built and on the allowable degree of time count errors. the flow chart below serves as a guide to selecting an optimum oscillation frequency adjustment procedure for the relevant system. s t a r t u s e 3 2 - k h z c l o c k c i r c u i t ? n o n o n o y e s y e s y e s y e s n o u s e 3 2 - k h z c l o c k c i r c u i t w i t h o u t r e g a r d t o i t s f r e q u e n c y p r e c i s i o n ? a l l o w a b l e t i m e c o u n t p r e c i s i o n i s o n o r d e r o f o s c i l l a t i o n f r e q u e n c y v a r i a t i o n s o f c r y s t a l o s c i l l a t o r * 1 p l u s f r e q u e n c y v a r i a t i o n s o f r e a l - t i m e c l o c k ? * 2 * 3 a l l o w a b l e t i m e c o u n t p r e c i s i o n i s o n o r d e r o f o s c i l l a t i o n f r e q u e n c y v a r i a t i o n s o f c r y s t a l o s c i l l a t o r * 1 p l u s f r e q u e n c y v a r i a t i o n s o f r e a l - t i m e c l o c k ? * 2 * 3 t o c o u r s e ( a ) t o c o u r s e ( b ) t o c o u r s e ( c ) t o c o u r s e ( d ) * 1) generally, crystal oscillators for commercial use are classified in terms of their center frequency depending on their load cap acitance (c l ) and further divided into ranks on the order of 10, 20, and 50ppm depending on the degree of their oscillation frequency variations. * 2) basically, the r 5c348a/b are configured to cause frequency variations on the order of 5 to 10ppm at normal temperature. * 3) time count precision as referred to in the above flow chart is applicable to normal temperature and actually affected by the te mperature characteristics and other properties of crystal oscillators.
r 5c348a/b 30 course (a) when the time count precision of each real-time clock is not to be adjusted, the crystal oscillator intended for use with that real-time clock may have any c l value requiring no presetting. the crystal oscillator may be subject to frequency variations which are selectable within the allowable range of time count precision. several crystal oscillators and real-time clocks should be used to find the center frequency of the crystal oscillators by the method described in ?.2 measurement of oscillation frequency?and then calculate an appropriate oscillation adjustment value by the method described in ?.4 oscillation adjustment circuit?for writing this value to the r 5c348a/b. course (b) when the time count precision of each real-time clock is to be adjusted within the oscillation frequency variations of the crystal oscillator plus the frequency variations of the real-time clock ics, it becomes necessary to correct deviations in the time count of each real-time clock by the method described in ?.4 oscillation adjustment circuit? such oscillation adjustment provides crystal oscillators with a wider range of allowable settings of their oscillation frequency variations and their c l values. the real-time clock ic and the crystal oscillator intended for use with that real-time clock ic should be used to find the center frequency of the crystal oscillator by the method described in ?.2 measurement of oscillation frequency?and then confirm the center frequency thus found to fall within the range adjustable by the oscillation adjustment circuit before adjusting the oscillation frequency of the oscillation circuit. at normal temperature, the oscillation frequency of the oscillator circuit can be adjusted by up to approximately 1.5ppm. course (c) course (c) together with course (d) requires adjusting the time count precision of each real-time clock as well as the frequency of 32.768-khz clock pulses output from the 32kout pin. normally, the oscillation frequency of the crystal oscillator intended for use with the real-time clocks should be adjusted by adjusting the oscillation stabilizing capacitors c g and c d connected to both ends of the crystal oscillator. the r 5c348a/b, which incorporate the c g and the c d , require adjusting the oscillation frequency of the crystal oscillator through its c l value. generally, the relationship between the c l value and the c g and c d values can be represented by the following equation: c l = c g c d + c s where ? s ?represents the floating capacity of the printed circuit board c g + c d the crystal oscillator intended for use with the r 5c348a/b is recommended to have the c l value on the order of 6 to 8pf. its oscillation frequency should be measured by the method described in ?.2 measurement of oscillation frequency? any crystal oscillator found to have an excessively high or low oscillation frequency (causing a time count gain or loss, respectively) should be replaced with another one having a smaller and greater c l value, respectively until another one having an optimum c l value is selected. in this case, the bit settings disabling the oscillation adjustment circuit (see ?.4 oscillation adjustment circuit? should be written to the oscillation adjustment register.
31 r 5c348a/b 2.4 oscillation adjustment cir cuit the oscillation adjustment circuit can be used to correct a time count gain or loss with high precision by varying the number of 1-second clock pulses once per 20 seconds. when such oscillation adjustment is not to be made, the oscillation adjustment circuit can be disabled by writing the settings of * , 0, 0, 0, 0, 0, * ?( * ?representing ??or ?? to the f 6 , f 5 , f 4 , f 3 , f 2 , f 1 , and f 0 bits in the oscillation adjustment circuit. conversely, when such oscillation adjustment is to be made, an appropriate oscillation adjustment value can be calculated by the equation below for writing to the oscillation adjustment circuit. 2.4-1 when oscillation f requency * 1 is higher than t arget f requency * 2 (there is a time count gain) oscillation adjustment value* 3 = (oscillation frequency ?target frequency + 0.1) oscillation frequency 3.051 10 ? = (oscillation frequency ?target frequency) 10 + 1 * 1) oscillation frequency: frequency of clock pulses output from the 32kout pin at normal temperature in the manner described in ?.2 measurement of oscillation frequency? * 2) target frequency: desired frequency to be set. generally, a 32.768-khz crystal oscillator has such temperature characteristics as to have the highest oscillation frequency at normal temperature. consequently, the crystal oscillator is recommended to have target frequency settings on the order of 32.768 to 32.76810khz (+3.05ppm relative to 32.768khz). note that the target frequency differs depending on the environment or location where the equipment incorporating the real-time clocks is expected to be operated. * 3) oscillation adjustment value: value that is to be finally written to the f 0 to f 6 bits in the oscillation adjustment register and is represented in 7-bit coded decimal notation. * 1) the c gout should have a capacitance ranging from 0 to 15pf. course (d) it is necessary to select the crystal oscillator in the same manner as in course (c) as well as correct errors in the time count of each real-time clock in the same manner as in course (b) by the method described in ?.4 oscillation adjustment circuit? r 5 c 3 4 8 a / b r f r d c d c g o s c i n o s c o u t 3 2 k h z v d d 1 0 9 8 v d d c g o u t * 1 another advisable way to select a crystal oscillator having an optimum c l value is to contact the manufacturer of the crystal oscillator intended for use with the r 5c348a/b. incidentally, the high oscillation frequency of the crystal oscillator can also be adjusted by adding an external oscillation stabilization capacitor c gout as illustrated in the diagram below. . .
r 5c348a/b 32 notes 1) oscillation adjustment does not affect the frequency of 32.768-khz clock pulses output from the 32kout pin. 2) oscillation adjustment value range: when the oscillation frequency is higher than the target frequency (causing a time count gain), an appropriate time count gain ranges from 3.05ppm to 189.2ppm with the settings of ?, 0, 0, 0, 0, 1, 0?to ?, 1, 1, 1, 1, 1, 1?written to the f 6 , f 5 , f 4 , f 3 , f 2 , f 1 , and f 0 bits in the oscillation adjustment register, thus allowing correction of a time count gain of up to +189.2ppm. conversely, when the oscillation frequency is lower than the target frequency (causing a time count loss), an appropriate time count gain ranges from +3.05ppm to +189.2ppm with the settings of ?, 1, 1, 1, 1, 1, 1 to ?, 0, 0, 0, 0, 1, 0?written to the f 6 , f 5 , f 4 , f 3 , f 2 , f 1 , and f 0 bits in the oscillation adjustment register, thus allowing correction of a time count loss of up to 189.2ppm. 2.4-2 when oscillation f requency is equal to t arget f requency (there is neither a time count gain nor a time count loss) writing the oscillation adjustment value setting of ?? ?1? 64? or 63?to the oscillation adjustment register disables the oscillation adjustment circuit. 2.4-3 when oscillation f requency is lo w er than t arget f requency (there is a time count loss) oscillation adjustment value* 3 = (oscillation frequency ?target frequency) oscillation frequency 3.051 10 ? = (oscillation frequency ?target frequency) 10 oscillation adjustment value calculations are exemplified below. (1) for an oscillation frequency of 32768.85hz and a target frequency of 32768.05hz: oscillation adjustment value = (32768.85 ?32768.05 + 0.1) / (32768.85 3.051 10 ? ) = (32768.85 ?32768.05) 10 + 1 = 9.001 = 9 in this instance, write the settings of ?, 0, 0, 1, 0, 0, 1?to the f 6 , f 5 , f 4 , f 3 , f 2 , f 1 , and f 0 bits in the oscillation adjustment register. thus, an appropriate oscillation adjustment value in the presence of any time count gain represents a distance from 01h. (2) for an oscillation frequency of 32763.95hz and a target frequency of 32768.05hz: oscillation adjustment value = (32763.95 ?32768.05) / (32763.95 3.051 10 ? ) = (32763.95 ?32768.05) 10 = ?1.015 = ?1 to represent an oscillation adjustment value of 41 in 7-bit coded decimal notation, subtract 41(29h) from 128(80h) to obtain 57h. in this instance, write the settings of ?, 0, 1, 0, 1, 1, 1?in the f 6 , f 5 , f 4 , f 3 , f 2 , f 1 , and f 0 bits in the oscillation adjustment register. thus, an appropriate oscillation adjustment value in the presence of any time count loss represents a distance from 80h. oscillation adjustment involves an adjustment differential of approximately 1.5ppm from the target frequency at normal temperature. . . . . . . . .
33 r 5c348a/b 3. oscillation halt sensing and suppl y v olta g e monitoring the oscillation halt sensing circuit is configured to record a halt in the oscillation of 32.768-khz clock pulses. the supply voltage monitoring circuit is configured to record a drop in supply voltage below a threshold voltage of 2.1 or 1.6 volts. for these functions, the real-time clock has two flag bits (ie. the xstp bit for the former and the vdet bit for the latter) in which 1 is set once and this setting is maintained until 0 is written. when the xstp bit is set to 1 for the oscillation halt sensing circuit, the vdet bit is reset to 0 for the supply voltage monitoring circuit. the relationship between the xstp and vdet bits is shown in the table below. the oscillation halt sensing circuit operates only when the ce pin is low. the sensing result is maintained after the ce pin changes from ??to ? (see ?.4 connection of ce pin?. xstp vdet conditions of supply voltage and oscillation 0 0 no drop in supply voltage below threshold voltage and no halt in oscillation 0 1 drop in supply voltage below threshold voltage and no halt in oscillation 1 * halt on oscillation s u p p l y v o l t a g e t h r e s h o l d v o l t a g e ( 2 . 1 o r 1 . 6 v o l t s ) s e t t i n g x s t p a n d v d e t b i t s t o 0 s e t t i n g x s t p a n d v d e t b i t s t o 0 i n t e r n a l i n i t i a l i z a t i o n p e r i o d ( 1 t o 2 s e c o n d s ) s e t t i n g v d e t b i t t o 0 o s c i l l a t i o n b y 3 2 . 7 6 8 - k h z c l o c k p u l s e s n o r m a l v o l t a g e d e t e c t o r s u p p l y v o l t a g e m o n i t o r i n g ( v d e t ) o s c i l l a t i o n h a l t s e n s i n g ( x s t p ) when the xstp bit is set to 1 in the control register 2, the (0), f 6 to f 0 , wale, dale, 12/24, clen2, test, ct 2 , ct 1 , ct 0 , vdsl, vdet, scratch1, scratch 2, scratch3, clen1, ctfg, wafg, and dafg bits are reset to 0 in the oscillation adjustment register, the control register 1, and the control register 2. the xstp bit is also set to 1 at power- on from 0 volts. when the ce pin is ??at power on from 0 volts, the xstp bit is undefined, and the above bits are undefined (see ?.4 connection of ce pin? . note that the xstp bit may be locked to 0 and the internal register broken upon instantaneous power-down.
r 5c348a/b 34 considerations in using oscillation halt sensing circuit be sure to prevent the oscillation halt sensing circuit from malfunctioning by preventing the following: 1) instantaneous power-down on the v dd 2) condensation on the crystal oscillator 3) on-board noise to the crystal oscillator 4) applying to individual pins voltage exceeding their respective maximum ratings in particular, note that the xstp bit may fail to be set to 1 in the presence of any applied supply voltage as illustrated below in such events as backup battery installation. further, give special considerations to prevent excessive chattering to pewer supply. v d d < supply voltage sensing circuit > the supply voltage monitoring circuit is configured to conduct a sampling operation during an interval of 7.8ms per second to check for a drop in supply voltage below a threshold voltage of 2.1 or 1.6 volts for the vdsl bit setting of 0 (the default setting) or 1, respectively, in the control register 2, thus minimizing supply current requirements as illustrated in the timing chart below. this circuit suspends a sampling operation once the vdet bit is set to 1 in the control register 2 i n t e r n a l i n i t i a l i z a t i o n p e r i o d ( 1 o r 2 s e c o n d s ) 7 . 8 m s 1 s t h r e s h o l d v o l t a g e o f 2 . 1 o r 1 . 6 v o l t s s e t t i n g 0 t o x s t p a n d v d e t b i t s s e t t i n g v d e t b i t t o 0 v d d x s t p s a m p l i n g o p e r a t i o n b y s u p p l y v o l t a g e m o n i t o r i n g c i r c u i t v d e t ( d 6 a t a d d r e s s f h )
35 r 5c348a/b 4. alarm and p eriodic interrupt the r 5c348a/b incorporate the alarm circuit and the periodic interrupt circuit that are configured to generate alarm signals and periodic interrupt signals, respectively, for output from the intr pin as described below. 1) alarm circuit the alarm interrupt circuit is configured to generate alarm signals for output from the intr, which is driven low (enabled) upon the occurrence of a match between current time read by the time counters (the day-of-week, hour, and minute counters) and alarm time preset by the alarm registers (the alarm_w registers intended for the day-of-week, hour, and minute digit settings and the alarm_d registers intended for the hour and minute digit settings). 2) periodic interrupt circuit the periodic interrupt circuit is configured to generate either clock pulses in the pulse mode or interrupt signals in the level mode for output from the intr pin depending on the ct 2 , ct 1 , and ct 0 bit settings in the control register 1. the above two types of interrupt signals are monitored by the flag bits (i.e. the wafg, dafg, and ctfg bits in the control register 2) and enabled or disabled by the enable bits (i.e. the wale, dale, ct 2 , ct 1 , and ct 0 bits in the control register 1) as listed in the table below. a l a r m _ d a l a r m _ w i n t r in this event, which type of interrupt signal is output from the intr pin can be confirmed by reading the wafg, dafg, and ctfg bit settings in the control register 2. flag bits enable bits alarm signals wafg bit wale bit (under control of alarm_w registers) (d1 at address fh) (d7 at address eh) alarm signals dale bit dale bit (under control of alarm_d registers) (d0 at address fh) (d6 at address eh) periodic interrupt signals ctfg bit ct 2 , ct 1 , and ct 0 bits ( d2 t o d0 at address eh) (d2 of internal address fh) (these bit settings of 0 disable the periodic interrupt circuit) at power-on, when the wale, dale, ct 2 , ct 1 , and ct 0 bits are set to 0 in the control register 1, the intr pin is driven high (disabled). when two or more types of interrupt signals are output simultaneously from the intr pin, the output from the intr pin becomes an or waveform of their negative logic. example: combined output of alarm interrupt signals under control of alarm_d and alarm_w registers
r 5c348a/b 36 4.1 alarm interrupt the alarm circuit is controlled by the enable bits (i.e. the wale and dale bits in the control register 1) and the flag bits (i.e. the wafg and dafg bits in the control register 2). the enable bits can be used to enable this circuit when set to 1 and to disable it when set to 0. when intended for reading, the flag bits can be used to monitor alarm interrupt signals. when intended for writing, the flag bits will cause no event when set to 1 and will drive high (disable) the alarm circuit when set to 0. the enable bits will not be affected even when the flag bits are set to 0. in this event, therefore, the alarm circuit will continue to function until it is driven low (enabled) upon the next occurrence of a match between current time and preset alarm time. the alarm function can be set by presetting desired alarm time in the alarm registers (the alarm_w registers for the day-of-week digit settings and both the alarm_w registers and the alarm_d registers for the hour and minute digit settings) with the wale and dale bits once set to 0 and then to 1 in the control register 1. note that the wale and dale bits should be once set to 0 in order to disable the alarm circuit upon the coincidental occurrence of a match between current time and preset alarm time in the process of setting the alarm function. i n t e r v a l ( 1 m i n u t e ) d u r i n g w h i c h a m a t c h b e t w e e n c u r r e n t t i m e a n d p r e s e t a l a r m t i m e o c c u r s i n t r p i n i n t r p i n s e t t i n g w a l e a n d d a l e b i t t o 1 m a t c h b e t w e e n c u r r e n t t i m e a n d p r e s e t a l a r m t i m e i n t h e d a y - o f - w e e k a n d h o u r s e t t i n g s m a t c h b e t w e e n c u r r e n t t i m e a n d p r e s e t a l a r m t i m e i n t h e d a y - o f - w e e k a n d h o u r s e t t i n g s m a t c h b e t w e e n c u r r e n t t i m e a n d p r e s e t a l a r m t i m e i n t h e d a y - o f - w e e k a n d h o u r s e t t i n g s s e t t i n g w a l e a n d d a l e b i t t o 0 s e t t i n g w a l e a n d d a l e b i t t o 1 m a t c h b e t w e e n c u r r e n t t i m e a n d p r e s e t a l a r m t i m e i n t h e d a y - o f - w e e k a n d h o u r s e t t i n g s s e t t i n g w a f g a n d d a f g b i t t o 0 s e t t i n g w a l e a n d d a l e b i t t o 1 s e t t i n g w a l e a n d d a l e b i t t o 0 m a x . 6 1 . 1 s
37 r 5c348a/b 4.2 p eriodic interrupt setting of the periodic selection bits (ct 2 to ct 0 ) enables periodic interrupt to the cpu. there are two waveform modes: pulse mode and level mode. in the pulse mode, the output has a waveform duty cycle of around 50%. in the level mode, the output is cyclically driven low and, when the ctfg bit is set to 0, the output is set to high (off). waveform mode, cycle and falling timing 1) pulse mode: 2-hz and 1-hz clock pulses are output in synchronization with the increment of the second counter as illustrated in the timing chart on the next page. 2) level mode: periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1 hour, and 1 month. the increment of the second counter is synchronized with the falling edge of periodic interrupt signals. for example, periodic interrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increment of the second counter as illustrated in the timing chart on the next page. 3) when the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20 seconds as follows: pulse mode: the ??period of output pulses will increment or decrement by a maximum of 3.784ms. for example, 1-hz clock pulses will have a duty cycle of 50 0.3784% level mode: a periodic interrupt cycle of 1 second will increment or decrement by a maximum of 3.784ms. ct2 ct1 ct0 description waveform mode interrupt cycle and fall timing 0 0 0 off (?? 0 0 1 fixed at low (?? 0 1 0 pulse mode * 1 2hz (duty cycle of 50%) 0 1 1 pulse mode * 1 1hz (duty cycle of 50%) 1 0 0 level mode * 2 once per 1 second (synchronized with second counter increment) 1 0 1 level mode * 2 once per minute (at 00 seconds of every minute) 1 1 0 level mode * 2 once per hour (at 00 minutes and 00 seconds of every hour) 1 1 1 level mode * 2 once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month) (default setting)
r 5c348a/b 38 s e t t i n g c t f g b i t t o 0 ( i n c r e m e n t o f s e c o n d c o u n t e r ) ( i n c r e m e n t o f s e c o n d c o u n t e r ) ( i n c r e m e n t o f s e c o n d c o u n t e r ) c t f g b i t i n t r p i n s e t t i n g c t f g b i t t o 0 5. 32-khz cloc k output for the r 5c348a, 32.768-khz clock pulses are output from the 32kout pin when either the clen1 bit in the control register 2 or the clen2 bit in the control register 1 is set to 0. when both the clen1 and clen2 bits are set to 0, the 32kout pin output is driven high (disabled) for the r 5c348b, 32.768-khz clock pulses are output from the 32kout pin regardless of such internal register settings. clen1 bit setting clen2 bit setting 32kout pin output 32kout pin output (d3 at address fh) (d4 at address eh) (for the r 5c348a) (for the r 5c348b) (nch. open drain output) (nch. open drain output) 1 1 off(?? clock pulses 0 (default) * clock pulses * 0 (default) for the r 5c348a, the 32kout pin output is synchronized with the clen1 and clen2 bit settings as illustrated in the timing chart below. m a x . 6 1 . 0 s m a x . 4 5 . 8 s c l e n 1 o r c l e n 2 b i t s e t t i n g 3 2 k o u t p i n o u t p u t ?level mode a p p r o x . 9 2 s c t f g b i t i n t r p i n ( i n c r e m e n t o f s e c o n d c o u n t e r ) r e w r i t i n g o f t h e s e c o n d c o u n t e r relation betw een the mode w a v ef or m and the ctfg bit ?pulse mode * ) in the pulse mode, the increment of the second counter is delayed by approximately 92 s from the falling edge of clock pulses. consequently, time readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second. rewriting the second counter will reset the other time counters of less than 1 second, driving the intr pin low.
39 r 5c348a/b 6. t ypical applications 6.1 t ypical p o wer cir cuit configurations sample circuit configuration 1 s y s t e m p o w e r s u p p l y r 5 c 3 4 8 a / b 3 2 . 7 6 8 k h z o s c i n o s c o u t v d d v s s * 1 sample circuit configuration 2 s y s t e m p o w e r s u p p l y r 5 c 3 4 8 a / b 3 2 . 7 6 8 k h z o s c i n o s c o u t v d d v s s * 1 * 1) install bypass capacitors for high-frequency and low- frequency applications in parallel in close vicinity to the r 5c348a/b . * 1) when using an or diode as a power supply for the r 5c348a/b, ensure that voltage exceeding the absolute maximum rating of v dd + 0.3 volts is not applied the so pin.
r 5c348a/b 40 6.2 connection of intr pin the intr pin follows the n-channel open drain output logic and contains no protective diode on the power supply side. as such, it can be connected to a pull-up resistor of up to 5.5 volts regardless of supply voltage. 6.3 connection of 32k out pin the 32kout pin follows the nch. open drain output and contains no protective diode on the power supply side. as such, it can be connected to a device with a supply voltage of up to 5.5 volts regardless of supply voltage, provided that such connection involves considerations for the supply current requirements of a pull-up resistor, which can be roughly calculated by the following equation: i = 0.5 (v dd or v cc ) / rp s y s t e m p o w e r s u p p l y r 5 c 3 4 8 a / b 3 2 . 7 6 8 k h z a b o s c i n o s c o u t v d d v s s i n t r b a c k u p p o w e r s u p p l y * 1 s y s t e m p o w e r s u p p l y ( v c c ) r 5 c 3 4 8 a / b 3 2 . 7 6 8 k h z a b o s c i n o s c o u t v d d v s s 3 2 k o u t b a c k u p p o w e r s u p p l y ( v d d ) r p * 1 * 1) depending on whether the intr pin is to be used during battery backup, it should be connected to a pull-up resistor at the following different positions: 1) position a in the left diagram when it is not to be used during battery backup. 2) position b in the left diagram when it is to be used during battery backup. * 1) depending on whether the 32kout pin is to be used during battery backup, it should be connected to a pull-up resistor at the following different positions: 1) position a in the left diagram when it is not to be used during battery backup. 2) position b in the left diagram when it is to be used during battery backup.
41 r 5c348a/b 6.4 connection of ce pin connection of the ce pin requires the following considerations: 1) the ce pin is configured to enable the oscillation halt sensing circuit only when driven low. as such, it should be driven low or open at power-on from 0 volts. 2) the ce pin should also be driven low or open immediately upon the host going down (see ?.5 considerations in reading and writing time count data?. 3) the reading function should be disrupted when the ce signal goes to ?ow?during read cycle. while, the upper 4 bits of the data might be written to the inner shift register when the ce signal goes to ?ow?during write cycle. (because the writing function is executed 4 bits by 4 bits.) in either case, after the ce signal returns to ?igh? no trouble will occur in the next read or write cycle. i / o c o n t r o l s c l k s i s o c e 2 4 3 7 l o w e r l i m i t o p e r a t i n g v o l t a g e f o r t h e c p u b a c k u p v o l t a g e 0 . 2 v d d m i n . 0 s m i n . 0 s m i n . 0 s v d d c e c p u r 5 c 3 4 8 a / b p e r i p h e r a l i c c e c e s c l k s i o s c l k s i s o c e 0 c e 1 s c l k d a t a 6.5 connection with 3-wire serial interface bus to connect the r 5c348a/b with 3-wire serial interface bus, shorten the si and so pins and connect them to the data line as shown in the figure below.
r 5c348a/b 42 x'ta l : 32.768khz (r 1 =30k typ.) (c l =6pf to 8pf) top t : 25?c output pins: open f r e q u e n c y c o u n t e r r 5 c 3 4 8 a / b 3 2 . 7 6 8 k h z o s c i n o s c o u t v d d v s s 3 2 k o u t s u p p l y v o l t a g e v d d ( v ) 0 1 0 0 . 2 0 . 4 0 . 6 0 . 8 1 2 3 4 5 6 t i m e k e e p i n g c u r r e n t i d d ( a ) ( c e = o p e n , o u t p u t = o p e n , t o p t = 2 5 ? c , r s 5 c 3 4 8 a ) s u p p l y v o l t a g e v d d ( v ) t i m e k e e p i n g c u r r e n t i d d ( a ) ( c e = o p e n , o u t p u t = o p e n , t o p t = 2 5 ? c ) 0 1 0 0 . 5 1 1 . 5 2 2 3 4 5 6 r 5 c 3 4 8 a r 5 c 3 4 8 b s c l k c l o c k f r e q u e n c y ( k h z ) 0 5 0 0 0 1 0 2 0 3 0 4 0 5 0 1 0 0 0 1 5 0 0 2 0 0 0 c p u a c c e s s c u r r e n t i d d ( a ) ( o u t p u t = o p e n , t o p t = 2 5 ? c ) v d d = 5 v v d d = 3 v o p e r a t i n g t e m p e r a t u r e t o p t ( ? c ) 6 0 4 0 0 0 . 5 1 1 . 5 2 2 0 0 2 0 4 0 6 0 8 0 6 0 t i m e k e e p i n g c u r r e n t i d d ( a ) ( c e = o p e n , o u t p u t = o p e n , t o p t = 2 5 ? c ) 7. t ypical characteristics test circuit 7.1 timekeeping current vs. suppl y v olta g e (with no 32-khz c loc k output) 7.2 timekeeping current vs. suppl y v olta g e (with 32-khz c loc k output) 7.3 cpu access current vs. sclk cloc k frequenc y 7.4 timekeeping current vs. operating t emperature (with no 32-khz c loc k output)
43 r 5c348a/b 7.5 oscillation frequenc y de viation vs. external c g e x t e r n a l c g ( p f ) 0 5 4 0 3 0 3 5 2 0 2 5 1 0 1 5 0 5 1 0 5 1 0 1 5 2 0 o s c i l l a t i o n f r e q u e n c y d e v i a t i o n ( p p m ) ( v d d = 3 v , t o p t = 2 5 ? c , e x t e r n a l c g = 0 p f a s s t a n d a r d ) 7.6 oscillation frequenc y de viation vs. suppl y v olta g e s u p p l y v o l t a g e v d d ( v ) 0 1 2 3 5 3 4 1 2 1 0 2 5 4 3 4 5 6 o s c i l l a t i o n f r e q u e n c y d e v i a t i o n ( p p m ) ( t o p t = 2 5 ? c , v d d = 3 v a s s t a n d a r d ) 7.7 oscillation frequenc y de viation vs. operating t emperature t e m p e r a t u r e t o p t ( ? c ) 6 0 4 0 2 0 0 1 4 0 1 0 0 1 2 0 6 0 8 0 4 0 2 0 2 0 0 2 0 4 0 6 0 8 0 1 0 0 o s c i l l a t i o n f r e q u e n c y d e v i a t i o n ( p p m ) ( v d d = 3 v , e x t e r n a l c g = 0 p f , t o p t = 2 5 ? c a s s t a n d a r d ) s u p p l y v o l t a g e v d d ( v ) 0 1 2 3 0 1 0 0 2 0 0 3 0 0 5 0 0 4 0 0 4 5 6 o s c i l l a t i o n s t a r t t i m e ( m s ) ( t o p t = 2 5 ? c ) v o l ( v ) 0 0 . 2 0 . 4 0 1 0 5 1 5 2 0 3 0 2 5 0 . 6 0 . 8 1 . 0 i o l ( m a ) ( t o p t = 2 5 ? c ) v d d = 3 v v d d = 5 v 7.8 oscillation star t time vs. suppl y v olta g e 7.9 v ol vs i ol (intr pin and 32k out pin of the r 5c348a) 10 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1.0 v ol (v) i ol (ma) v dd =5v v dd =3v (topt=25 ? c) 7.10 v ol vs i ol (32k out pin of the r 5c348b)
r 5c348a/b 44 8. t ypical software-based operations 8.1 initialization at p o wer -on s t a r t x s t p = 1 ? p o w e r - o n n o n o y e s y e s w a r n i n g o f b a c k u p b a t t e r y r u n - d o w n s e t o s c i l l a t i o n a d j u s t m e n t r e g i s t e r a n d c o n t r o l r e g i s t e r s 1 a n d 2 , e t c . v d e t = 0 ? * 1 * 2 * 4 * 3 8.2 writing of time and calendar data w a i t f o r 3 1 s w r i t e t o t i m e c o u n t e r a n d c a l e n d a r c o u n t e r * 1 * 2 * 1) after power-on from 0 volts, the start of oscillation and the process of internal initialization require a time span on the ord er of 1 to 2 seconds, so that access should be done after the lapse of this time span or more. * 2) the xstp bit setting of 0 in the control register 1 indicates power-on from backup battery and not from 0 volt. the xstp bit m ay fail to be set to 1 in the presence of any excessive chattering in power supply in such events as installing backup battery. should there be any possibil ity of this failure occurring, it is recommended to initialize the r 5c348a/b regardless of the current xstp bit setting. for further details, see ?. oscillation halt sensing and supply voltage monitoring? * 3) this step is not required when the supply voltage monitoring circuit is not used. * 4) this step involves ordinary initialization including the oscillation adjustment register and interrupt cycle settings. * 1) this step of waiting is detailed in ?.5 considerations in reading and writing time data? * 2) any writing to the second counter will reset divider units lower than the second digits. the r 5c348a/b may also be initialized not at power-on but in the process of writing time and calendar data.
45 r 5c348a/b 8.3 reading time and calendar data 8.3-1 ordinar y process of reading time and calendar data w a i t f o r 3 1 s r e a d f r o m t i m e c o u n t e r a n d c a l e n d a r c o u n t e r * 1 8.3-2 basic process of reading time and calendar data synchroniz ed with p er iodic interr upt c t f g = 1 ? g e n e r a t e i n t e r r u p t i n c p u w r i t e , 1 , , 1 , , 0 , 1 , 1 t o c o n t r o l r e g i s t e r 2 s e t p e r i o d i c i n t e r r u p t c y c l e s e l e c t i o n b i t s y e s n o r e a d f r o m t i m e c o u n t e r a n d c a l e n d a r c o u n t e r * 1 * 2 * 3 o t h e r i n t e r r u p t p r o c e s s e s * 1) this step of waiting is detailed in ?.5 considerations in reading and writing time data? * 1) this step is intended to select the level mode as a waveform mode for the periodic interrupt function. * 2) if this step is completed within 1 second, the step of waiting described in ?.3-1 ordinary process of reading time and calendar data?above need not be conducted. this step is detailed in ?.5 considerations in reading and writing time data? * 3) this step is intended to set the ctfg bit to 0 in the control register 2 to cancel an interrupt to the cpu.
r 5c348a/b 46 8.3-3 applied process of reading time and calendar data synchroniz ed with p er iodic interr upt time data need not be read from all the time counters when used for such ordinary purposes as time count indication. this applied process can be used to read time and calendar data with substantial reductions in the load involved in such reading. c t f g = 1 ? g e n e r a t e i n t e r r u p t t o c p u w r i t e , , , , 0 , 1 , 0 , 0 t o c o n t r o l r e g i s t e r 1 w r i t e , 1 , , 1 , , 0 , 1 , 1 t o c o n t r o l r e g i s t e r 2 n o y e s n o y e s w r i t e , 1 , , 1 , , 0 , 1 , 1 t o c o n t r o l r e g i s t e r 2 u s e p r e v i o u s m i n u t e , h o u r , d a y - o f - w e e k , a n d d a y - o f - m o n t h d a t a o t h e r i n t e r r u p t p r o c e s s e s r e a d m i n u t e , h o u r , d a y - o f - w e e k , a n d d a y - o f - m o n t h c o u n t e r s * 1 * 2 * 4 * 3 s e c o n d d i g i t = 0 0 ? for time indication in ?ay-of-month, day-of-week, hour, minute, and second?format: * 1) this step is intended to select the level mode as a waveform mode for the periodic interrupt function. * 2) if this step is completed within 1 second, the step of waiting described in ?.3.-1 ordinary process of reading time and calen dar data?above need not be conducted. this step is detailed in ?.5 considerations in reading and writing time data? * 3) this step is intended to read time data from all the time counters only in the first session of reading time data after writing time data. * 4) this step is intended to set the ctfg bit to 0 in the control register 2 to cancel an interrupt to the cpu.
47 r 5c348a/b c t f g = 1 ? g e n e r a t e i n t e r r u p t t o c p u w r i t e , 1 , , 1 , , 0 , 1 , 1 t o c o n t r o l r e g i s t e r 2 s e t p e r i o d i c i n t e r r u p t c y c l e s e l e c t i o n b i t s y e s n o p e r i o d i c i n t e r r u p t p r o c e s s o t h e r i n t e r r u p t p r o c e s s e s * 1 * 2 w a f g o r d a f g = 1 ? g e n e r a t e i n t e r r u p t t o c p u w a l e o r d a l e = 1 w r i t e , 1 , , 1 , , 1 , 0 , 1 t o c o n t r o l r e g i s t e r 2 w a l e o r d a l e = 0 y e s n o c o n d u c t a l a r m i n t e r r u p t s e t a l a r m m i n u t e , h o u r , a n d d a y - o f - w e e k r e g i s t e r s * 1 * 2 * 3 o t h e r i n t e r r u p t p r o c e s s e s 8.4-2 alar m interr upt 8.4 interrupt pr ocess 8.4-1 p er iodic interr upt * 1) this step is intended to select the level mode as a waveform mode for the periodic interrupt function. * 2) this step is intended to set the ctfg bit to 0 in the control register 2 to cancel an interrupt to the cpu. * 1) this step is intended to once disable the alarm interrupt circuit by setting the wale and dale bits to 0 in anticipation of the coincidental occurrence of a match between current time and preset alarm time in the process of setting the alarm interrupt function. * 2) this step is intended to enable the alarm interrupt function after completion of all alarm interrupt settings. * 3) this step is intended to once cancel the alarm interrupt function by writing the settings of ,1, ,1, ,1,0,1?and ,1, ,1, ,1,1,0?to the alarm_w registers and the alarm_d registers, respectively.
r 5c348a/b 48 0 . 5 1 5 4 . 0 0 . 3 2 . 8 0 . 2 1 0 6 2 . 9 + 0 . 3 - 0 . 1 0 . 1 2 7 + 0 . 1 - 0 . 0 5 0 . 5 5 0 . 2 0 t o 1 0 0 . 1 0 . 1 5 0 . 1 m 0 . 2 0 . 1 1 . 1 0 . 1 + 0 . 1 - 0 . 0 5 1 . 3 0 m a x . 0 . 1 5 + 0 . 1 - 0 . 0 5 0 . 5 0 . 2 0 t o 1 0 0 . 1 0 . 1 0 . 1 0 . 1 m 0 . 2 0 . 1 1 . 1 5 0 . 1 0 . 9 m a x . 0 . 5 0 1 5 6 . 4 0 . 2 4 . 4 0 . 2 1 0 6 3 . 5 0 0 . 2 ?rs5c348a/b (10-pin ssop) p a cka ge dimensions (unit : mm) ?rv5c348a/b (10-pin ssop-g)
49 r 5c348a/b 0 . 3 2 . 7 m a x . 4 . 0 0 . 1 2 . 0 0 . 0 5 8 . 0 0 . 1 1 . 7 5 0 . 1 5 . 5 0 . 0 5 3 . 9 6 . 7 1 2 . 0 0 . 3 u s e r d i r e c t i o n o f f e e d . 1 . 5 + 0 . 1 0 1 . 5 + 0 . 1 0 2 . 0 m a x . 4 . 4 8 . 0 0 . 1 3 . 2 1 . 7 5 0 . 1 5 . 5 0 . 0 5 1 2 . 0 0 . 3 0 . 3 4 . 0 0 . 1 2 . 0 0 . 0 5 u s e r d i r e c t i o n o f f e e d . t aping specifica tions (unit : mm) the rv5c348a/b have one designated taping direction. the product designations for the taping components are ?v5c348a-e2?and ?v5c348b-e2? ? rv5c348a/b (10-pin ssop-10g) the rs5c348a/b have one designated taping direction. the product designations for the taping components are ?s5c348a-e2?and ?s5c348b-e2? ? rs5c348a/b (10-pin ssop)
ricoh company, ltd. electronic devices division headquarters 13-1, himemuro-cho, ikeda city, osaka 563-8501, japan phone +81-727-53-6003 fax +81-727-53-2120 yokohama office (international sales) 3-2-3, shin-yokohama, kohoku-ku, yokohama city, kanagawa 222-8530, japan phone +81-45-477-1697 fax +81-45-477-1694 ?1695 http://www.ricoh.co.jp/lsi/english/ ricoh corporation electronic devices division san jose office 1996 lundy avenue, san jose, ca 95131, u.s.a. phone +1-408-944-3306 fax +1-408-432-8375 http://www.ricoh-usa.com/semicond.htm

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